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PIC18F1230/1330

2009 Microchip Technology Inc.

DS39758D-page 257

22.2

Extended Instruction Set

In addition to the standard 75 instructions of the PIC18

instruction set, PIC18F1230/1330 devices also provide

an optional extension to the core CPU functionality.

The added features include eight additional instruc-

tions that augment indirect and indexed addressing

operations and the implementation of Indexed Literal

Offset Addressing mode for many of the standard

PIC18 instructions.

The additional features of the extended instruction set

are disabled by default. To enable them, users must set

the XINST Configuration bit.

The instructions in the extended set (with the exception

of CALLW, MOVSF and MOVSS) can all be classified as

literal operations, which either manipulate the File

Select Registers, or use them for indexed addressing.

Two of the instructions, ADDFSR and SUBFSR, each

have an additional special instantiation for using FSR2.

These versions (ADDULNK and SUBULNK) allow for

automatic return after execution.

The extended instructions are specifically implemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

Dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

Function Pointer invocation

Software Stack Pointer manipulation

Manipulation of variables located in a software

stack

A summary of the instructions in the extended instruction

set is provided in Table 22-3. Detailed descriptions are

provided in Section 22.2.2 “Extended Instruction

Set”

. The opcode field descriptions in Table 22-1

(page 216) apply to both the standard and extended

PIC18 instruction sets.

22.2.1

EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed

arguments, using one of the File Select Registers and

some offset to specify a source or destination register.

When an argument for an instruction serves as part of

indexed addressing, it is enclosed in square brackets

(“[ ]”). This is done to indicate that the argument is used

as an index or offset. The MPASM Assembler will

flag an error if it determines that an index or offset value

is not bracketed.

When the extended instruction set is enabled, brackets

are also used to indicate index arguments in byte-

oriented and bit-oriented instructions. This is in addition

to other changes in their syntax. For more details, see

Section 22.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”

TABLE 22-3:

EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note:

The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in the assem-

bler. The syntax for these commands is

provided as a reference for users who may

be reviewing code that has been

generated by a compiler.

Note:

In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text

and

going

forward,

optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands

Description

Cycles

16-Bit Instruction Word

Status

Affected

MSb

LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add Literal to FSR

Add Literal to FSR2 and Return

Call Subroutine using WREG

Move zs (source) to 1st word

fd (destination) 2nd word

Move zs (source) to 1st word

zd (destination) 2nd word

Store Literal at FSR2,

Decrement FSR2

Subtract Literal from FSR

Subtract Literal from FSR2 and

Return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

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